Abstract: We demonstrate a 40 Gb/s self-synchronizing, all-optical packet
clockrecovery circuit designed for efficient packet-mode traffic. The circuit
locks instantaneously and enables sub-nanosecond packet spacing due to the
low clock persistence time. A low-Q Fabry-Perot filter is used as a passive
resonator tuned to the line-rate that generates a retimed clock-resembling
signal. As a reshaping element, an optical power-limiting gate is
incorporated to perform bitwise pulse equalization. Using two preamble
bits, the clock is captured instantly and persists for the duration of the data
packet increased by 16 bits. The performance of the circuit suggests its
suitability for future all-optical packet-switched networks with reduced
transmission overhead and fine network granularity.
Abstract: We present an all-optical circuit that performs header separation and insertion to 10 Gb/s variable
length optical packets using a packet clockrecovery circuit to control a 2x2 optical exchange bypass switch.
Abstract: In this paper, we demonstrate clock extraction from
10 Gb/s asynchronous short data packets. Successful clock
acquisition is achieved from data packets arriving at time
intervals of only 1.5 ns, irrespective of their precise phase
relation. The clockrecovery circuit used consists of a Fabry-
Perot filter (FPF) and a non-linear UNI gate and requires very
short time for synchronization.
Abstract: This paper reviews the work performed under the
European ESPRIT project DO_ALL (Digital OpticAL Logic
modules) spanning from advanced devices (semiconductor optical
amplifiers) to all-optical modules (laser sources and gates) and
from optical signal processing subsystems (packet clockrecovery,
optical write/store memory, and linear feedback shift register) to
their integration in the application level for the demonstration of
nontrivial logic functionality (all-optical bit-error-rate tester and
a 2 2 exchange–bypass switch). The successful accomplishment
of the project˘s goals has opened the road for the implementation
of more complex ultra-high-speed all-optical signal processing
circuits that are key elements for the realization of all-optical
packet switching networks.
Abstract: We demonstrate a simple all-optical technique to detect the beginning of a packet for packet-rate
synchronization. It employs a packet clockrecovery unit and a SOA and it requires no special data encoding to operate.
Abstract: We demonstrate an all-optical clock and data recovery
circuit for short asynchronous data packets at 10-Gb/s line
rate. The technique employs a Fabry–P{\'e}rot filter and an ultrafast
nonlinear interferometer (UNI) to generate the local packet
clock, followed by a second UNI gate to act as decision element,
performing a logical AND operation between the extracted clocks
and the incoming data packets. The circuit can handle short
packets arriving at time intervals as short as 1.5 ns and arbitrary
phase alignment.
Abstract: We present optical clock and data recovery for 10 Gb/s asynchronous packets. The original data are
sampled with an optical gate powered by clock packet, generated with a novel packet clockrecovery circuit.
Abstract: We present and evaluate a compact, all-optical Clock and Data
Recovery (CDR) circuit based on integrated Mach Zehnder interferometric
switches. Successful operation for short packet-mode traffic of variable
length and phase alignment is demonstrated. The acquired clock signal rises
within 2 bits and decays within 15 bits, irrespective of packet length and
phase. Error-free operation is demonstrated at 10 Gb/s.
Abstract: In this paper, we demonstrate optical transparency
in packet formatting and network traffic offered by all-optical
switching devices. Exploiting the bitwise processing capabilities
of these “optical transistors,” simple optical circuits are designed
verifying the independency to packet length, synchronization
and packet-to-packet power fluctuations. Devices with these attributes
are key elements for achieving network flexibility, fine
granularity and efficient bandwidth-on-demand use. To this end, a
header/payload separation circuit operating with IP-like packets,
a clock and data recovery circuit handling asynchronous packets
and a burst-mode receiver for bursty traffic are presented. These
network subsystems can find application in future high capacity
data-centric photonic packet switched networks.
Abstract: Digital optical logic circuits capable of performing bit-wise signal processing are critical building blocks for the realization of future high-speed packet-switched networks. In this paper, we present recent advances in all-optical processing circuits and examine the potential of their integration into a system environment. On this concept, we demonstrate serial all-optical Boolean AND/XOR logic at 20 Gb/s and a novel all-optical packet clockrecovery circuit, with low capturing time, suitable for burst-mode traffic. The circuits use the semiconductor-based ultrafast nonlinear interferometer (UNI) as the nonlinear switching element. We also present the integration of these circuits in a more complex unit that performs header and payload separation from short synchronous data packets at 10 Gb/s. Finally, we discuss a method to realize a novel packet scheduling switch architecture, which guarantees lossless communication for specific traffic burstiness constraints, using these logic units.
Abstract: In this paper, we review recent advances in ultrafast optical time-domain technology with emphasis on the use in optical packet switching. In this respect, several key building blocks, including high-rate laser sources applicable to any time-division-multiplexing (TDM) application, optical logic circuits for bitwise processing, and clock-recovery circuits for timing synchronization with both synchronous and asynchronous data traffic, are described in detail. The circuits take advantage of the ultrafast nonlinear transfer function of semiconductor-based devices to operate successfully at rates beyond 10 Gb/s. We also demonstrate two more complex circuits-a header extraction unit and an exchange-bypass switch-operating at 10 Gb/s. These two units are key blocks for any general-purpose packet routing/switching application. Finally, we discuss the system perspective of all these modules and propose their possible incorporation in a packet switch architecture to provide low-level but high-speed functionalities. The goal is to perform as many operations as possible in the optical domain to increase node throughput and to alleviate the network from unwanted and expensive optical-electrical-optical conversions.
Abstract: We demonstrate a compact, all-optical, packet clock and data recovery circuit that uses integrated MZIs. Clock is acquired within 2 bits irrespective of packet length and phase alignment. Error-free operation is demonstrated at 10 Gb/s.
