Abstract: In this paper, a novel configuration is proposed for
the implementation of an almost all-optical switcharchitecture
called the schedulingswitch, which when combined with appropriate
wait-for-reservation or tell-and-go connection and flow
control protocols provides lossless communication for traffic
that satisfies certain smoothness properties. An all-optical 2 2
exchange/bypass (E/B) switch based on the nonlinear operation
of a semiconductor optical amplifier (SOA) is considered as the
basic building block of the schedulingswitch as opposed to active
SOA-based space switches that use injection current to switch
between ON and OFF states. The experimental demonstration of
the optically addressable 2 2 E/B, which is summarized for
10–Gb/s data packets as well as synchronous digital hierarchy
(SDH)/STM-64 data frames, ensures the feasibility of the proposed
configuration at high speeds, with low switching energy and low
losses during the scheduling process. In addition, it provides
reduction of the number of required components for the construction
of the schedulingswitch, which is calculated to be 50% in the
number of active elements and 33% in the fiber length.
Abstract: We present an architecture for implementing optical
buffers, based on the feed-forward-buffer concept, that can truly
emulate input queuing and accommodate asynchronous packet
and burst operation. The architecture uses wavelength converters
and fixed-length delay lines that are combined to form either a
multiple-input buffer or a shared buffer. Both architectures are
modular, allowing the expansion of the buffer at a cost that grows
logarithmically with the buffer depth, where the cost is measured
in terms of the number of switching elements, and wavelength
converters are employed. The architectural design also provides
a tradeoff between the number of wavelength converters and their
tunability. The buffer architectures proposed are complemented
with scheduling algorithms that can guarantee lossless communication
and are evaluated using physical-layer simulations to
obtain their performance in terms of bit-error rate and achievable
buffer size.
Abstract: We present an architecture for implementing optical
buffers, based on the feed-forward-buffer concept, that can truly
emulate input queuing and accommodate asynchronous packet
and burst operation. The architecture uses wavelength converters
and fixed-length delay lines that are combined to form either a
multiple-input buffer or a shared buffer. Both architectures are
modular, allowing the expansion of the buffer at a cost that grows
logarithmically with the buffer depth, where the cost is measured
in terms of the number of switching elements, and wavelength
converters are employed. The architectural design also provides
a tradeoff between the number of wavelength converters and their
tunability. The buffer architectures proposed are complemented
with scheduling algorithms that can guarantee lossless communication
and are evaluated using physical-layer simulations to
obtain their performance in terms of bit-error rate and achievable
buffer size.
Abstract: Digital optical logic circuits capable of performing bit-wise signal processing are critical building blocks for the realization of future high-speed packet-switched networks. In this paper, we present recent advances in all-optical processing circuits and examine the potential of their integration into a system environment. On this concept, we demonstrate serial all-optical Boolean AND/XOR logic at 20 Gb/s and a novel all-optical packet clock recovery circuit, with low capturing time, suitable for burst-mode traffic. The circuits use the semiconductor-based ultrafast nonlinear interferometer (UNI) as the nonlinear switching element. We also present the integration of these circuits in a more complex unit that performs header and payload separation from short synchronous data packets at 10 Gb/s. Finally, we discuss a method to realize a novel packet schedulingswitcharchitecture, which guarantees lossless communication for specific traffic burstiness constraints, using these logic units.