Abstract: This paper reviews the work performed under the
European ESPRIT project DO_ALL (Digital OpticAL Logic
modules) spanning from advanced devices (semiconductor optical
amplifiers) to all-optical modules (laser sources and gates) and
from optical signalprocessing subsystems (packet clock recovery,
optical write/store memory, and linear feedback shift register) to
their integration in the application level for the demonstration of
nontrivial logic functionality (all-optical bit-error-rate tester and
a 2 2 exchange–bypass switch). The successful accomplishment
of the projectĘs goals has opened the road for the implementation
of more complex ultra-high-speed all-opticalsignalprocessing
circuits that are key elements for the realization of all-optical
packet switching networks.
Abstract: Recent advances in the all-opticalsignalprocessing
domain report high-speed and nontrivial
functionality directly implemented in the optical
layer. These developments mean that the alloptical
processing of packet headers has a future.
In this article we address various important control
plane issues that must be resolved when
designing networks based on all-optical packetswitched
Abstract: Digital optical logic circuits capable of performing bit-wise signalprocessing are critical building blocks for the realization of future high-speed packet-switched networks. In this paper, we present recent advances in all-opticalprocessing circuits and examine the potential of their integration into a system environment. On this concept, we demonstrate serial all-optical Boolean AND/XOR logic at 20 Gb/s and a novel all-optical packet clock recovery circuit, with low capturing time, suitable for burst-mode traffic. The circuits use the semiconductor-based ultrafast nonlinear interferometer (UNI) as the nonlinear switching element. We also present the integration of these circuits in a more complex unit that performs header and payload separation from short synchronous data packets at 10 Gb/s. Finally, we discuss a method to realize a novel packet scheduling switch architecture, which guarantees lossless communication for specific traffic burstiness constraints, using these logic units.